1. Statement of the Technical Field
This document relates to electronic interconnection structures, and more particularly to microstructures which facilitate high-speed interconnections between certain types of devices for communicating and sharing data.
2. Description of the Related Art
There is a general and continuing need for faster data transport between electronic devices disposed on substrates. One commonly utilized method for increasing data rates between two devices disposed on a substrate involves providing a plurality of parallel data link channels. By increasing the number of data link channels, the data throughput limitations of each individual link can be overcome. But the data rate improvements which have been obtained by using parallel data links are reaching their limit. This is due to the growing number of required I/O pads, the increase in power dissipated as a result of a growing number of on chip driver and receiver circuits (and associated limits with regard to how much heat can be removed from the device), and the difficulty of routing traces and compensating for faults.
Digital devices such as central processing units (CPUs), graphics processing units (GPUs), and field programmable gate arrays (FPGAs) have been moving to increasingly higher data rates for serial I/O (e.g., Xilinx Virtex®-7 HT FPGAs at 28 Gb/s). Serial data links have inherent problems with distortion as rates increase, requiring in many cases equalization stages on chip. At the present time high speed data links in modules, on boards, and on backplanes are typically accomplished with controlled impedance printed circuit board (PCB) transmission lines or copper to/from fiber optic translators. Most commercial devices launch data from the component with copper interconnects and use an external fiber optic translator. But interconnects made with PCB transmission lines are exposed to the lossy characteristics of the substrate upon which they are built. Advanced substrate materials such as Liquid Crystal Polymer (LCP) have helped to extend the frequency range (and bit rates) that can be handled. Still, the methods that have been used before are now becoming a limiting factor given the advances in chip speeds.